This invention relates to a system for recovering a clock signal synchronized with received digital data, and more particularly to a digital timing recovery system for recovering a clock signal synchronized with received non-return-to-zero (NRZ) data.
A common format for transmitting digital data is the so-called non-return-to-zero (NRZ) format, in which one data bit is separated from an adjacent data bit only by a time relationship as defined by a master clock. Thus, a series of zeros would appear as a continuous low signal, whereas a series of ones would appear as a continuous high signal. Only when there is a data transition--i.e., a change from a zero to a one, or a one to a zero--is the boundary between one data bit an an adjacent data bit apparent.
When such a data stream is presented to a receiver, it is necessary to recover or produce a clock signal that is synchronized with the data transitions in order to properly interpret the data. The classical technique for recovering a clock signal synchronized with an input stream of digital data, especially NRZ data, is by use of an analog phase-locked loop. Analog phase-locked loop circuitry, which is well known in the art, typically comprises a phase detector to compare the phase of the received digital data with that of a clock signal; a low pass filter to convert an error signal from the phase detector to an error voltage; and a voltage controlled oscillator (VCO) having an output frequency that is controlled by the error voltage generated by the low pass filter.
Numerous problems are associated with the design, use, and manufacture of analog phase-locked loop circuits. For example, the VCO may be an extremely complex circuit, and the number of components that must be handled to fabricate a phase-locked loop circuit on a printed circuit board can significantly increase manufacturing costs. Moreover, analog phase-locked loop circuits have problems associated with the stability of the oscillator, resulting in undesirable "jitter" appearing in the output clock signal. Design techniques aimed at reducing clock jitter, however, create an oscillator with very limited lock range, meaning the phase-locked loop is only capable of locking onto data within a very narrow frequency spectrum. Also, component or voltage supply variations due to aging and temperature changes may contribute to the stability problems by creating drift in the oscillator frequency and error voltage.
Digital phase-locked loops have also been employed in the prior art. For example, Malek, U.S. Pat. No. 3,983,498 (1976), discloses an oscillator, programmable frequency divider, phase detector, and data transition detector. The transition detector is used to generate a pulse of defined width at each data transition. The oscillator is used to generate a fixed frequency signal, which frequency is then divided by a programmable frequency divider down to the desired clock frequency. To synchronize the phase of the clock signal with the data transitions, the phase of the data is compared with the phase of the oscillator in the phase detector, and depending upon whether the clock phase leads or lags the data phase, the divisor of the programmable divider is adjusted so as to advance or retard the clock phase to synchronize it with the data transitions.
The problems with digital phase-lock loops of the type disclosed in Malek are that the adjustments to the clock phase are made at every data transition. This tends to cause excessive jitter in the clock output signal. Moreover, the divisor of the programmable frequency divider is always changed by the same amount, thereby defining a fixed rate at which the clock signal may be brought into phase with the data transitions regardless of the amount of phase error that exists when the signals are first compared. Hence, a long access time results.